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This
lab, launched in 1999, addresses modeling, synthesis and optimization
techniques for the electronic design automation (EDA) of embedded
computing systems, especially Systems-on-Chip (SoC). Its goal is to
develop and/or disseminate EDA tools, not only for hardware design
(e.g. synthesis and simulation tools at the architectural, RTL and
logic levels), but also for embedded software development (e.g. cross
compilers, assemblers, link editors, debuggers, simulators). The lab
activities are oriented to comply with the requirements of modern SoCs
(low-power, real-time and compact code) and with distinct
microelectronic implementation alternatives and styles (e.g. ASIC,
FPGA).
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